When newer processor systems and architectures are introduced, it is desirable to be able to continue to use programs developed for older processor systems. For this purpose, emulators are used, which imitate older processor systems on the newer ones, and make it possible to execute program code created for an older processor, also called original processor, on the newer one, also called target processor. Emulators are typically themselves programs run on the target processor and dynamically transform instruction sequences for the original processor into instruction sequences for the target processor to then efficiently run them directly on the target processor.
As part of the translation of the instructions, address operators of instructions, e.g., load instructions and jump instructions must be correctly translated. In an addressing method provided in many processor architectures and frequently used, an address is defined by the specification of a base register and an offset. The address is calculated at run time as the sum of the content of the specified base register and the offset. Instructions using this addressing method are also called “instructions with base register-relative addressing.” For conciseness, the term “base register-relative instruction” is also common.
The address space reachable by such a base-register relative instruction is frequently smaller than the maximum addressable address space based on the bit width of the register. S/390 processors from IBM, for example, have an available bit width of 32 bits. An address space with addresses of 24 bit or 31 bits long can be selected so that the possible address space comprises a range from 0 to 224−1 or from 0 to 231−1. The address space is also configured cyclically in such a manner that calculated addresses that reach past the edge of the address space are wrapped around and onto the address space. This can be done, for example, by dividing the address that results from the content of the address register plus the offset by the size of the address space and using the remainder resulting from this division, which then lies in the address space, as the effective address. Such a calculation is referred to as a modulo operation or a wrap-around calculation.
Due to the generally larger addressing widths of newer processor architectures, newer processors do not necessarily support the smaller address spaces of older processor systems. Different-sized address spaces can be problematic for the emulation of program code, however. A calculated address for a load or jump instruction, for example, that lies outside the address space of the original processor, but can be represented in the larger address space of the target processor, differs in the emulated program from the effective address determined taking into account the wrap-around on the original processor. To nevertheless calculate the address correctly in an emulation, it is necessary to insert additional instructions into the translated program code, by which the smaller size of the address space in the original processor is taken into account. This can be done, for instance, by first determining the address in a temporary register as the sum of the content of the base register and the offset in a first instruction and, in a second instruction, then emulating the wrap-around into a smaller address space by using an operation of the modulo 2n type, where n indicates the length of the addresses in the smaller address space of the original processor. Then a jump or a data access can be executed via the address in the temporary register. The base register-relative instruction is indeed emulated semantically correctly in this manner, but the emulation requires two additional program instructions for each instruction, whereby it is slowed down.
A method and a device for generating a modulo address to access a ring buffer is disclosed in U.S. Pat. No. 5,918,252. As inputs, the method and the device take a length of the ring buffer, a current address of the ring buffer and a distance between the current address and the next address to be generated. During operation, the current address is decomposed into a base address and a distance relative to the base access.
A unit for generating mixed modulo addresses with several inputs is disclosed in U.S. Pat. No. 5,790,443. That unit effectively adds a subset of these inputs to a reduced modulo, while other inputs are simultaneously added in a full modulo to the partial sum of the reduced-modulo inputs.
It could therefore be helpful to provide methods for converting base register-relative instructions in an emulation with which the different sizes of the address spaces of the original and the target processor are correctly taken into account and which simultaneously allows an effective emulation with as few additional instructions as possible.